Cross Architecture Performance Prediction
Given the rapid evolution of modern computing architectures, the time required to understand, benchmark, and model each new chip design can be daunting. Application performance depends on both the underlying hardware, as well as the efficiency of the application software stack. Since overall efficiency can depend strongly on hardware-specific software optimizations, early performance predictions can enable valuable software modifications be- fore the target architecture is even in production. In this work, we explore a completely data-driven approach to hardware performance prediction. We leverage leadership-scale super-computing resources to build and train empirical models, with limited profiling data, without modifying any original source code. We employ both neural-architecture search (NAS) optimizations and active learning to automatically design and train deep learning models for the prediction of IPC (instructions per cycle) across two separate NVIDIA GPU architectures (P100 to V100). Although the massively-parallel approach certainly yields improved performance over simple empirical models, the accuracy of IPC predictions still falls short of expected real-world requirements.
Yuliana's advisors are Prof. Ian Foster and Prof. Henry Hoffmann